LIDAR ASIC with SPAD Based Pixel Array

  • SPAD-based pixel array
  • Integrated Analog Front-end (AFE), Time-to-Digital converters (TDC) and readout circuitry
  • On-chip PLL and thermal sensor
  • 10 mm x 9 mm chip size
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High Dynamic Range Imager

  • 4 MP array resolution
  • 10.8 µm square pixels
  • Lateral Overflow pixel architecture for high intra-scenic dynamic range
  • 180 FPS at full resolution
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Large Stitched X-Ray CMOS Image Sensor

  • 30 µm square pixels
  • 6 repeating segments
  • 854 H x 1200 V
  • 2-MHz pixel clock rate
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163 MP High Resolution CMOS Image Sensor

  • 163 MP with APS-C format
  • 1.5 µm square pixels
  • 20 frames per second (full resolution)
  • On-chip ADC
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Large Pixel Flexible Test Array

  • 8-16 µm range of pixel pitch options
  • 0.3 MP to 1 MP available array format resolutions
  • Flexible/programmable timing and level signaling control
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Large Pixel 110nm BSI Flexible Test Array

  • 10-20 µm pixel pitch
  • Flexible/programmable pixel timing and level signaling control
  • Standard test package and characterization system platform
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133 MP High Resolution CMOS Image Sensor

  • 133 MP
  • Super-Hi Vision
  • 2.45 µm square pixels
  • 60 frames per second
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High Dynamic Range (HDR) CMOS Image Sensor

  • 10.8 µm square pixels
  • 100 dB dynamic range
  • 30 to 60 frames per second
  • On-chip, column parallel 12-bit ADCs
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1280 x 1024 CTIA ROIC

  • 15 µm CTIA pixel pitch
  • 60 fps with external CDS timing support
  • 8-channel, 12-bit, 21 MSPS pipeline ADCs
  • 16:1, 336 Mbit/sec serializer with LVDS outputs 
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12-Bit, 75 MSPS ADC IP Block

 
  • Fully differential pipeline architecture
  • 85 mW @ 1.5 V
  • > 68 dB SNR
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