Custom High-Speed I/O IP Library

  • Full complement of padframe I/O for custom high-speed data transport circuitry
  • 10 Gbit/sec I/O
  • Digital I/O
  • Power, ground, analog
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X-Band Oscillator/VCPS

  • 10.2-GHz center frequency
  • 500-MHz bandwidth
  • Low-noise amplifier
  • Bandpass filter
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Custom Receiver IP for Image Sensor Output Data

  • 8 channel with line valid detection circuitry
  • Custom DLL design for 1.2 Gbit/sec to 600 MBit/sec input data format support
  • Integrated digital block for output data formatting to image data compression IP block
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SiGe TIA-LA

  • 12 channel
  • 3.6 Gbit/sec/channel
  • Programmable output swing, bandwidth via serial interface
  • CML outputs
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8K Ultra-HDTV CMOS Image Sensor

  • 7840 x 4360 (32 MP)
  • Ultra-HDTV
  • 3.8 µm 4T pixel
  • 60 frames per second
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SiGe VCSEL Driver

  • 12 channel
  • 3.6 Gbit/sec/channel
  • Programmable DACs via I2C interface
  • CML Inputs
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IR Pixel Development Platform

  • Third-generation for 10 µm pixel pitch development
  • Support for various pixel types
  • Flexible pixel timing and biasing control
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640 x 320 CTIA Array ROIC

  • 15 µm CTIA pixel pitch
  • 60 fps with external CDS timing support
  • On-chip, low-drift temperature sensor
  • 4-channel, 12-bit, 21 MSPS pipeline ADCs
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1280 x 1024 Snapshot ROIC

  • 12.5 µm CTIA pixel pitch
  • 120 fps with in-pixel CDS timing support
  • Column-parallel accelerated ramp ADC
  • 600 Mbit/sec serializer with LVDS outputs
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Glucose Monitor with RF Link

  • 2 large pixels (420 µm x 320 µm)
  • Low noise true CDS readout
  • 45 dB SNR at 80% full well
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