Analysis and Simulation of CTIA-based Pixel Reset Noise

This paper describes an approach for accurately simulating the reset noise of CTIA-based pixels. Using a circuit simulator to find the reset noise of a CTIA based pixel is not straightforward, due to the noise sampling and charge redistribution after the reset switch opens. Read more

CMOS Integration of Capacitive, Optical, and Electrical Interconnects

We present a 90 nm test chip integrating proximity communication, optics using external lasers and photodiodes, and CML electronics on a single CMOS chip which can route data at multi-Gb/s rates through any combination of its three interconnect interfaces. Read more

CMOS lmager with Embedded Analog Early Image Processor

We present a high quality computational CMOS imager with integrated early image processing general-purpose filter. The early processor identifies in real-time areas of interest within the field of view, and reduces data volume and data-bandwidth to the external processor.  Read more

Optical Transceiver Chips Based on Co-Integration of Capacitively Coupled Proximity Interconnects and VCSELs

Combining the strengths of both proximity communication and optical communication, a new hybrid input–output (I/O) platform delivers on-chip bandwidth off-chip and over distance. We demonstrate, for the first time, a four-channel hybrid I/O interface by integrating proximity communication and vertical-cavity surface-emitting-laser-based parallel optical interconnects on the same commercial 90-nm complementary metal–oxide–semiconductor platform. Read more

A Low Phase Noise 10 GHz Optoelectronic RF Oscillator Implemented Using CMOS Photonics

The emerging wireless communications standards at higher frequencies, especially toward 60 and 80 GHz, are challenged by the availability of cost-effective high performance oscillators. Since the bandwidth of a wireless communications system is heavily dependent on the phase noise of the local oscillator, spectral efficiency at these frequencies is limited to a fraction of that achieved in cellular, WiFi, and WiMax applications using available local oscillators (LO). Read more

Ultra High Light Shutter Rejection Ratio Snapshot Pixel Image Sensor ASIC for Pattern Recognition

The ultra high light shutter rejection ratio snapshot pixel image sensor ASIC is designed for detecting moving objects without motion artifacts. This chip can be integrated into the fast moving pattern recognition system, such as machine vision and robot control system. Read more

A Two-Dimensional Array Imager Demonstrating Active Reset Suppression of kTC-Noise

The design and performance of a two-dimensional photodiode visible imager with a means of reducing the reset noise below the kTC limit is discussed. This active reset scheme uses feedback with an opamp per column in order to increase the gain and therefore the noise reduction over that seen for ordinary “soft” or “flushed” reset. Read more

A Smart CMOS Imager with On-Chip High-Speed Windowed Centroiding Capability

Low-power, high-speed, accurate computation of centroid from a pre-defined window in the image plane is important for a number of space-based and commercial applications. These include object tracking in robotic systems [1], autonomous navigation, image compression [2], and document copyright protection [3], as well as space guidance and navigation systems [4], and deep-space optical communication systems that require accurate and stable beam pointing for high speed data transfer [5]. Read more

A High Speed, 240 Frame/s, 4 Megapixel CMOS Sensor

The paper describes a large format 4 Megapixel (2352 x 1728) sensor with on-chip parallel 10 bit ADCs. The chip size is 20 x 20 mm with 7 μm pixel pitch.The paper describes a large format 4 Megapixel (2352 x 1728) sensor with on-chip parallel 10 bit ADCs. The chip size is 20 x 20 mm with 7 μm pixel pitch. It achieves a high frame rate of 240 frames/s delivering 9.75 Gbit of data per second. The sensor also features an additional fixed pattern noise cancellation circuitry. Read more

Dynamically Reconfigurable Imager for Real-Time Staring Vision Systems

Design and characterization of a high-performance multi-acuity, multi-window dynamically reconfigurable vision (DRV) CMOS imager for real-time staring vision systems is presented. By carrying out on-focal-plane image preprocessing, the imager chip simultaneously supports low-resolution large field-of-view (FOV) scan and high-resolution narrow FOV tracking. Read more