Analysis and Enhancement of Low-Light-Level Performance of Photodiode-Type CMOS Active Pixel Imagers Operated with Sub-Threshold Reset

Noise in photodiode-type CMOS active pixel sensors (APS) is primarily due to the reset (kTC) noise at the sense node [1], since it is difficult to implement in-pixel correlated double sampling for a 2-D array. Read more

CMOS Sum & Difference Imager with On-Chip Charge-Leakage Compensation

This paper presents a new technique for implementing a low-power CMOS imager with simultaneous on-chip computation of the difference and sum of two successive frames. Existing difference imagers are susceptible to errors due to collection (by the sense element and in-pixel storage node) of photo-generated charge that diffuses from the photo-active pixel area during integration of the second frame. Read more

A Low-Light to Sunlight, 60 Frames/s, 80 kpixel CMOS APS Camera-on-a-Chip with 8b Digital Output

In the last several years, many CMOS APS photodiode image sensors have been developed for consumer and commercial use. These sensors typically rely on illumination levels on the order of 100 Lux (a well-lit room) for optimal operation at video frame rates. Read more

A High Speed, 500 Frames/s, 1024 x 1024 CMOS Active Pixel Sensor

The paper presents a high-speed (500 f/s) large-format 1K x 1K 8 bit 3.3V CMOS active pixel sensor (APS) with 1024 ADCs integrated on chip. The sensor achieves an extremely high output data rate of over 500 Mbytes per second and a low power dissipation of 350 mW at the 66 MHz master clock rate.  Read more

A Single Chip CMOS APS Digital Camera

There is an enormous demand for low power, highly integrated image sensor systems. CMOS based Active Pixel Sensor (APS) technology enables this progression. We demonstrate a very low power, highly integrated, programmable, complete digital camera-on-a-chip based on CMOS APS technology. Read more

Megapixel CMOS APS with Analog and Digital Readout

This paper reports the operation and performance of two 1024 x 1024-element CMOS active pixel image sensors (APS) with on-chip analog-to-digital conversion (ADC), analog and digital readout signal chain electronics. Previously, a 256 x 256-element CMOS APS with on chip timing and control was demonstrated by JPL with excellent image quality. Read more

Simulation of High Density CCD Imager Structures

Simulation results are presented for design of high-density imager in the form of 3-phase BCCD with three layers of polysilicon gates. To assure a high charge transfer efficiency we have considered a process with a dual gate dielectric having 350Å Si02 layer covered with 650Å Si3N4 layer. Read more