Member of Technical Staff (2 Positions Available)

Position Summary:

  • This position will participate and contribute to chip design solutions by completing all project tasks as assigned by the VP of Engineering. Chip design projects include analog and digital custom integrated circuit layout in fine line CMOS and BiCMOS processes; interact closely with the Circuit Design Engineers in order to optimize the performance of integrated circuits. 

Primary Responsibilities:

  • Specific electrical engineering duties include the following:
    •  Overall design of highly sophisticated architecture
    •  Circuit design on transistor level with Cadence Schematic Capture
    •  Simulation with analog simulators like Spectre, Berkley design suites, AMS co-simulator, etc.
    •  Layout with Cadence Virtuoso
    •  Design verification with Calibre and Assura: Layout vs. schematic check and Design rule check
    •  Parasitic extraction with QRC and hand calculation
    •  Floor planning
    •  Top level integration, schematic and layout with Cadence Mixed Signal Front andBack (MSFB)
    •  Full chip mixed simulation involving: Co-simulation Verilog, Berkley design, suites, and AMS co-simulator
    •  Design review reports
    •  Tape out to foundry
    •  Device characterization for actual silicon
  • Additional duties include the following:
    • Layout design of integrated circuits
    • Layouts of digital/analog clock for designs using TSMC 0.35 µm technology process
    • Perform DRC and LVS
    • Create layout of signal processor for image sensors using AMS 0.35 µm technology process.
    • Must be able to design using various other fab design rules and processes.
    • Apply multiple integrated circuit development skills between chip architecture and chip bring-up

Requirements & Minimum Education Level:

  • M.S. in Computer or Electrical Engineering or related science

Experience:

  • Must have demonstrated IC design experience involving: 1) CMOS technology process 2) Clean Room procedure and wafer fabrication and 3) Cadence design tools and full-chipmixed simulation in Verilog
  • Employer will accept design experience either through employment, internship, or coursework relevant to a Masters degree in electrical engineering or similar

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