Design Flow

The design flows and methodologies used by Forza Silicon are based on a specification driven methodology. Analog and digital design flows occur simultaneously, and converge into an integration flow, which produces the database for manufacturing the chip.

The design specification is used to define system architecture. The architecture is decomposed into analog and digital blocks. The system architecture is used to determine the initial floor plan layout and chip size.

Analog Design Flow

Based on the system architecture, each analog block has its own block architecture. Schematics capture the block architecture within the constraints of the specifications.

Analog design, layout and verification tools simulate and analyze a custom analog integrated circuit (IC) design. Waveform signals are simulated and analyzed in different modes to characterize noise, power utilization, timing, etc.
br> Simulation is done with estimated loading across corners to verify specification compliance.

Digital/Logic Design Flow

Design intent is captured in Verilog Register-Transistor Language (RTL). Forza Silicon designers have extensive experience generating synthesizable RTL, creating self-checking test benches and performing RTL simulations.

Synthesis requires conversion of RTL to a gate-level Netlist implementation, which is targeted to a specific foundry process and library. Timing constraints, such as clock information, input arrival times, output required times, input driving cells, output loading, false paths, multi-cycle paths, etc., are defined at a detail level.

Forza designers use test benches from RTL simulations to verify the correctness of the gate-level Netlist.

Integration Design Flow

All of the schematics and IP blocks are brought together to form a top-level chip schematic. A simulation is performed to determine proper operation and specification compliance.

Floor Planning requires integrating trade-offs and constraints to map the logical design into the physical domain, including:

• Physical block partitioning
• Assignment of block sizes and pinouts
• Timing budgets and block constraint generation
• Power and clock distribution planning

Place & Route incorporates timing constraints similar to those used during static timing analysis and synthesis, including:

• Automated placement
• Clock tree synthesis
• Signal and power routing
• Signal integrity

Parasitic resistance and capacitance components result from interconnects, and they are not intended to be part of the circuit function. RC Extraction is needed to support simulation of the effect due to “parasitic” elements. Parasitic components are back annotated into the physical layout and re-simulated to ensure proper operation.

Physical verification involves LVS (Layout v. Schematic) and DRC (Design Rule Checker) audits. These checks eliminate design layout errors before tape-out. This stage produces a database for release to a foundry to manufacture the chip.

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