CMOS Sum & Difference Imager with On-Chip Charge-Leakage Compensation

This paper presents a new technique for implementing a low-power CMOS imager with simultaneous on-chip computation of the difference and sum of two successive frames. Existing difference imagers are susceptible to errors due to collection (by the sense element and in-pixel storage node) of photo-generated charge that diffuses from the photo-active pixel area during integration of the second frame. Our proof-of-concept imager uses a new unbalanced differential signal chain to provide 17 fold reduction in leakage error in the frame difference output. The resulting INL is < 1 % over most of the illumination range. Error reduction is achieved without noticeable increase either of fixed-pattern-noise (FPN) or of read noise, preserving high image quality. Power dissipation in the 256 x 256 imager is measured to be only 18 mW.

CMOS Sum & Difference Imager with On-Chip Charge-Leakage Compensation