133 MPixel 60 fps CMOS Image Sensor with 32-Column Shared High-Speed Column-Parallel SAR ADCs

To realize next-generation highly realistic sensation broadcasting systems, the research and development of 8K ultrahigh-definition television (UHDTV) systems have been promoted. To realize 8K video cameras, 33Mpixel sensors [1-2] and a full-resolution camera system that uses three 33Mpixel sensors [3] have been reported. Read more

A 4-Side Tileable Back Illuminated 3D-Integrated Mpixel CMOS Image Sensor

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost [1]. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. Read more

High Frame-Rate Global Shutter Image Sensor with Dual-Reset Branch SAR ADC Architecture

This paper describes a high-speed 1.3 Mpix global shutter CMOS image sensor with a column parallel SAR ADC readout. In order to achieve the row time requirements at the maximum frame rate, the SAR ADC utilizes a novel dual reset branch architecture. Read more

BSI Low Light Level CMOS Image Sensor Employing P-type Pixel

A backside illuminated (BSI) CMOS imager technology optimized for night vision applications (NVCMOSTM) has been developed employing a hole-based p-type pixel (pMOS). Benefits of the technology include lower dark current and reduced random telegraph noise (RTN) as compared to conventional electron-based n-type pixels (nMOS). Read more

RF Design Issues and Challenges in a CMOS Image Sensor Process

This paper presents design issues and challenges encountered when designing RF transceiver circuits in a 0.18 µm 3.3 V/1.8 V CMOS Image Sensor (CIS) process. Even before putting down a transistor to design, there are infrastructure challenges to overcome. Read more

Design of Analog Readout Circuitry with Front-end Multiplexing for Column Parallel Image Sensors

This paper reports progress in our column parallel analog signal chain design strategy, utilizing varying degrees of parallelism for CMOS image sensors.  In [1] we investigated the trade-offs for different choices of parallelism and presented an analytical model for optimization of an endoscopic sensor. Read more

Single Slope ADC with On-chip Accelerated Continuous-time Differential Ramp Generator for Low Noise Column-Parallel CMOS Image Sensor

This paper presents a 12-bit single slope ADC architecture that uses an on-chip ramp generator for low noise column-parallel CMOS image sensor. An on-chip continuous-time ramp generator is used instead of a discrete-time implementation. Read more

Design of a PTC-Inspired Segmented ADC for High-Speed Column-Parallel CMOS Image Sensor

This paper presents a successive approximation ADC (SAR) architecture that takes advantage of the signal-dependent photon shot-noise characteristic of an image sensor. The multi-segmented successive approximation ADC (MS-SAR) applies the sub-ranging technique, where each segment’s conversion step size is scaled according to the photon transfer curve (PTC) of a given pixel. Read more

A 2.5 inch, 33 Mpixel, 60 fps CMOS Image Sensor for UHDTV Application

We have developed a 7840 x 4360 pixel, 60 fps CMOS image sensor fabricated in 0.18 µm 1P4M process that is used for an Ultra High Definition Television (UHDTV) camera system.  Read more

CMOS lmager with Embedded Analog Early Image Processor

We present a high quality computational CMOS imager with integrated early image processing general-purpose filter. The early processor identifies in real-time areas of interest within the field of view, and reduces data volume and data-bandwidth to the external processor.  Read more