This paper presents design issues and challenges encountered when designing RF transceiver circuits in a 0.18 µm 3.3 V/1.8 V CMOS Image Sensor (CIS) process. Even before putting down a transistor to design, there are infrastructure challenges to overcome. These challenges include getting the appropriate models from the foundry, setting up the design environment, generating parasitic extraction decks, and modeling the inductors. After overcoming the huddles of getting the design environment in place, we adopted several general design practices to realize RF transceiver circuits in a CIS process.
June 01, 2013