This paper reports the operation and performance of two 1024 x 1024-element CMOS active pixel image sensors (APS) with on-chip analog-to-digital conversion (ADC), analog and digital readout signal chain electronics. Previously, a 256 x 256-element CMOS APS with on chip timing and control was demonstrated by JPL with excellent image quality. The work reported in this presentation is to investigate feasibility of large format APS, the effect of design rule scaling on APS performance, and the demonstration of digital APS readout with on-chip column-parallel single slope ADC.
The two APS imagers reported here include both photodiode-type and photogate-type pixels, with in-pixel source followers, row selection and reset transistors. The chips have been implemented in a 0.55 µm n-well process, have a 11.0 µm pixel pitch, and operate from a +3.3 V supply. They are intended for slow-scan space science applications requiring 100 kpix./sec to 5 Mpix./sec data rate.