This paper presents a real-time calibration scheme for a 14-bit multi-segment, single slope ADC architecture using a 290 MHz current DAC based on-chip ramp generator. The ramp generator enables the creation of a ramp with multiple slopes, allowing scaling of the ADC resolution according to a given system’s shot noise limited curve.This flexibility allows various system tradeoffs to be made without the need for silicon redesign. For example, frame-rate, power dissipation, resolution, and other system-level parameters can be traded off to optimize performance for different applications, pixel characteristics or operating modes. Non-idealities resulting from the multi-slope ramp degrade the converter’s linearity. A real-time calibration scheme was developed that greatly improved the converter’s linearity and proved to be an enabling technology for the chosen ADC architecture.
01 June, 2013